RESPONSIBILITIES: 

• Lead a team and perform project planning, estimation, tracking, mentoring, reviews, etc. 
• Plan and conduct reviews and work with other NBIO groups 
• Ensure that metrics are established to measure the IP quality 
• Evaluation/review of all new or existing methods, comparing them to established procedures and  standards both technical and non-technical and champion where applicable 
• Plan and conduct test centric Post Mortem evaluation/review 
• Develop and implement design quality control and improvement processes 
• Constantly look to improve design productivity 
• Leading the Team's development of leading edge innovative IP level features 
• Manage staff career development, goal planning and day-to-day problem resolution 
• Hands-on resolution of problems and priority calls 
• Carry milestone definition on complex ASIC/SoC designs - management of 
•   "gate" criteria 
• Represent the team in the AMD engineering community 
• Experience with industry standard protocols and interfaces such as AXI4, ACE-lite and/or PIPE 
• Resolve complex problems involving: 
  •  advanced static timing analysis and formal verification 
  • RTL Linting and CDC checking 
  • ASIC/SoC Design flows and methodology implementations and enhancements 
  • IP/sub-system/SoC problems 

• 10+ years professional experience including SOC/PCIe/Fabrics/MMU Design 
• Communication skills: excellent oral, written and presentation skills 
• Leadership experience in productivity improvement 
• Familiar with aspects of IP Design Goals and Milestones 
• Working knowledge of Verilog, System Verilog, C/C++, Perl/Python 
• Good understanding of PCIe, Hyper-Transport (HT) protocols 
• At least 3 years of management experience with proven record of dealing with hiring, performance management and coaching of employees 
• Chipset and Fusion architecture and design knowledge (Northbridge, FCH, DDR Interface, Memory controllers) 
• DFT, Debug knowledge 
• Self-starter and quick learner and able to achieve successful outcomes in a non-hierarchical environment, with minimal supervision or direction 
• Detail oriented; ability to multitask through planning/organizing 
• Project management skills and experience 

• University graduate (BE/BTECH/MTECH) in Electronics or Computer engineering