- 21萬-28萬/年
- 北京
- |
- 3年以上
- |
- 本科
- |
- 全職
職位誘惑: 年終獎金,五險一金,老板nice,年底雙薪,股票期權(quán),年度旅游,技術(shù)領(lǐng)先,成長空間大,技能培訓,福利好,天天下午茶,節(jié)日禮物
發(fā)布時間: 2018-05-08發(fā)布
職位描述
Principal Duties and Responsibilities:
Design the analog layout in power management products. Design includes low & high voltage CMOS layout design and DRC, LVS verification.
Finish analog IC top layout and DRC, LVS verification independently.
Knowledge, Skills, and Abilities Required:
? BSEE with knowledge in analog IC layout design.
? Preferably with 3 to 5 years working experience in CMOS process
? Good knowledge in design of IC analog top and block layout.
?? Able to work in a team with good written and communication skills.
? Able to finish project layout independently.
? Preferably with high voltage BCD process experience.
職位發(fā)布者
北京凹凸維系電子開發(fā)有限公司
HR
7天
簡歷處理用時
99%
滬公網(wǎng)安備31011502017136號