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Design Verification Engineer

收藏職位
  • 我要分享
  • 15萬(wàn)-25萬(wàn)/年
  • 上海
  • |
  • 應(yīng)屆生/在校生
  • |
  • 碩士
  • |
  • 全職

職位誘惑: 年終獎(jiǎng)金,五險(xiǎn)一金,福利好,成長(zhǎng)空間大

發(fā)布時(shí)間: 2021-02-19發(fā)布

職位描述

Job Description
ASIC design verificationengineer responsible for the verification and evaluation of digital circuits inhigh-speed data communication ICs. The candidate will be involved inverification plan development, test environment setup, modeling, test casedevelopment and execution. He/She will be responsible for block and /or chiplevel verification. The IC products to work with include Ethernet/AutomotivePHY/Switch SoC, high speed SerDes based PHYs, and so on.
Job Requirement
MS in EE or CE with VLSIemphasis. Graduate from reputable university with competitive GPA or classranking. Graduate course work in VLSI design, digital circuit theory, logicdesign or computer architecture. Exposure to graduate school projects in ASIC designor verification.
Must be proficient in thefollowing skills:
Fundamental concepts in digital logic design 
Understand ASIC verification flows and methodologies 
Verilog and SystemVerilog/SystemC/Vera 
Strong Perl and Tcl scripting 
UNIX Shell scripting (Csh, Bash)
Highly desirable skills:
Formal verification 
Low power design
MATLAB and C/C++ based system simulation andevaluation
DSP function hardware implementation knowledge

Good personal communicationskills and team working spirit. Hardworking and motivated to be part of ahighly competent design team.

職位發(fā)布者

Nancy Wang

HR

7天

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100%

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