Job Description
Logic Synthesis: memory integration, RTL sanity check, std. cell mapping, timing/power/area optimization, scan stitching & formal verification. 
Design for Test: DFT spec and partition, BSD/JTAG/MBIST logic generation and insertion, scan chain insertion and ATPG pattern generation/simulation/ verification, DFT constraints development. 
Physical Implementation: floorplanning, power planning, placement, clock tree synthesis, timing closure, routing, SI prevention, DRC fixing, DFM correctness and etc. 
Physical Verification: Xtalk analysis, power/ESD/EM analysis, DRC/LVS/ANT/ERC check and etc. 
Tapeout: low power ERC signoff, timing ECO and signoff, power signoff, design tapeout and etc. 

Job Qualifications
BS or MS in EE or CS from first class universities, major in VLSI, logic or CPU design. Good GPA required. 
Hands-on experience in IC design industry or in college is preferred.
Detail oriented, self-motivated and a team player. Good verbal and written communication skills.