Verification is the number one bottleneck in SOC designs today. Synopsys is uniquely positioned to offer the most complete verification solution in market today. VCS is the Platform for Synopsys verification flow. It incorporates a suite of built-in high performance next generation technologies for test bench automation, assertion based verification, coverage closure, etc., which are needed for verifying challenging multi-million gate designs. Synopsys Verification IP provides verification engineers’ access to the industry latest protocols, interfaces and memories required to verify their SoC designs. Deployed across thousands of projects, Synopsys VIP supports AMBA, PCI Express, USB, MIPI, DDR, LPDDR, HDMI, Ethernet, SATA/SAS, Fibre Channel, OCP and others. Synopsys Verification IP supports advanced SystemVerilog-based testbenches including built-in methodology support for UVM and VMM. It includes features to simplify testbench development, verification planning, functional coverage and improved simulation runtime.
As a Senior AE for Verification, candidate will be responsible for successful deployment of Synopsys verification flow to a growing customer base in Asia Pacific. The AE responsibilities include onsite deployment of industry leading automation and verification technologies, creation of technical collateral, defining new methodology, and product support, testing and writing specifications for enhancement. Candidate will be responsible to interact with and support customers, sales, and marketing, and help analyze and resolve complex verification issues for customers’ cutting edge ASIC designs. The position offers a great opportunity to grow by learning state-of-art verification flows from Synopsys.
 
Requirements: 
MS or PhD majored in EE with more than 5 years of IC design/verification experiences. Good knowledge of high-level design methodologies and strong communication skills are required. Ability to work with customers and R&D teams is important. Real project experiences in ASIC/SoC verification are required. Proficient with HDL (Verilog/VHDL), HVL(e/Vera/SystemVerilog), C/C++, Unix, and having a strong understanding of ASIC design flows, VLSI, and/or CAD-engineering. Experience on VMM/OVM/UVM and knowledge of SNPS verification IPs are preferred. Knowledge and experience on protocols like MIPI, PCIE and USB will be a plus.