Senior Application Engineer (Front-end Verification)
- 25萬-30萬/年
- 北京
- |
- 1-3年
- |
- 碩士
- |
- 全職
職位誘惑: 年終獎(jiǎng)金,五險(xiǎn)一金,股票期權(quán)
發(fā)布時(shí)間: 2021-01-12發(fā)布
職位描述
Position Description:
- Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, simulation Emulation and Acceleration products.
- Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
- Train, ramp-up and accompany customer project.
- Conduct basic and advanced trainings, presentations and demos as necessary.
- Providing technical expertise to address clients’ queries, which need expert involvement.
- Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.
Position Requirements:
- 4~8 years’ experience in the following areas:
- Design experience in Verilog/VHDL for IP or SoC chip level.
- HW verification with knowledge of System Verilog/VHDL and HDL simulators
- FPGA prototyping project experience
- Experience with hardware emulator or accelerator is a big advantage
- Advanced Verification Methodology like UVM is a plus
- Knowledge of Unix and Linux is highly desired
- Strong verbal and written communication skills in English
- Strong teamwork skills with good human relationship
職位發(fā)布者
cadence hr
Sr.Manager&BP
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Cadence
領(lǐng)域: 移動(dòng)手持,消費(fèi)電子,通信網(wǎng)絡(luò)
規(guī)模: 500-1000人
主頁: http://www.cadence.com.cn/
工作地址:
北京,東城區(qū)北三環(huán)東路36號(hào)
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