This is technical role for design and implementation of CMOS power ICs. And will contribute at many levels of the development cycle including circuit design, simulation, modeling, verification and bench characterization.

Principal Duties and Responsibilities:
1. Responsible for analog IC products (power management) block design.
2. Complete design of low & high voltage CMOS circuit, SPICE simulation.
3. Co-work with Layout Engineer for layout and responsible for IC design.
4. Work closely with AE for test, debug and MP support.

Knowledge, Skills, and Abilities Required:
1. Master degree above, major in Microelectronics or Electronic and Information Engineering is preferred.
2. Have knowledge and design experience in power management IC.
3. Solid understanding of design and analysis of transistor-level low-power design in BCD and HVCMOS process.
4. Relevant experience in switching power supplies including buck/boost converter and battery charger.
5. Understanding the feedback system and stability analysis in time and freq domains.
6. Familiar with layout for optimal analog performance and have understanding of device physics.
7. Be good at IC design tools, good English language skills in written listening and speaking.
8. Must work well in a team environment and be self-motivated and pro-active. Diligent, serious-minded, logistic, Innovative.
職能類別：集成電路IC設(shè)計(jì)/應(yīng)用工程師