CPU DV Engineer
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Responsibilities:
You will work in fast growing team and will participate in one or several of below tasks
1 Define/develop the verification environment for the core, core submodule, and full chip
2 Create verfication test plans
3 Develop/run/debug testcases and function coverage
4 Use a wide set of verification tools and platforms, including formal verification tool, emulator
5 Develop/maintain regression infrastruction for core DV
 
Qualifications:
1 M.S. or B.S. in Computer Science or Computer Engineering or Electrical Engineering
2 Experience in at least one of following areas:
  - Computer architecture knowledge
  - Verification environment development in Verilog, Specman, System Verilog UVM/OVM
  - Verification and debug experience including testcase writing/generation, checker
    development, coverage analysis, failure debug, root cause analysis
  - Formal verification
  - Instruction set simulator (ISS)
  - Assembly language programming, code generation, or other low-level software experience.
3 Programming experience in at least one language: C/C++, Perl, Python, Ruby, etc.
4 Strong communication and collaboration skills