- 30萬-50萬/年
- 成都
- |
- 3年以上
- |
- 碩士
- |
- 全職
職位誘惑: 五險一金,福利好,技術(shù)領(lǐng)先,成長空間大,通訊津貼,交通補助,節(jié)日禮物,技能培訓(xùn)
發(fā)布時間: 2019-02-27發(fā)布
職位描述
JOB DESCRIPTION:
- Chip-level and module-level architecture definition and design
- Module-level synthesis and timing analysis
- Document write for design spec and report
- FPGA/silicon debug on related modules
QUALIFICATIONS:
- BSEE with minimum 3-year experience on SOC/MCU design
- Proficiency in Verilog RTL coding and digital IC design
- Solid knowledge on ARM architecture ,AMBA2.0 and AMBA3.0
- Experience on DMA/DDR/USB/Serdes is plus
- Knowledge on Mix-signal design is plus
- Familiar with low-power design is preferred
- Strong teamwork and communication ability.
職位發(fā)布者
李曉露
HR
7天
簡歷處理用時
100%
滬公網(wǎng)安備31011502017136號