Synthesis and Signoff Engineer
- 25萬-50萬/年
- 上海
- |
- 工作經(jīng)驗(yàn)不限
- |
- 本科
- |
- 全職
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職位誘惑: 股票期權(quán),年終獎(jiǎng)金,技術(shù)領(lǐng)先,成長空間大,五險(xiǎn)一金,福利好,老板nice,節(jié)日禮物
發(fā)布時(shí)間: 2019-05-17發(fā)布
職位描述
Job Description
· Responsible for block /full-chip MCMM physical aware synthesis
· Co-work with physical design team to drive the best PPA
· Responsible for SDC finalizing
· Responsible for timing ECO and signoff
· Responsible for UPF writing and VCLP low power signoff
· Responsible for formal verification
· Responsible for power evaluation
· Be a highly-valued member through excellent collaboration and teamwork with other teams
Qualifications
· BS degree or higher in EE, CE, or CS
· 2+ years hands-on experience as DFT/Synthesis/STA engineers
· Strong SDC writing and debugging experience
· Strong physical aware synthesis experience
· Strong timing ECO and STA signoff experience
· Strong Formal verification experience
· Good knowledge to UPF and low power check
· Strong debugging and analytical skills
· English documents reading
· Good programming in Perl/Python, TCL and Shell programming
Self-motivated, team work, and good communication skills
職位發(fā)布者
魯冬梅
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