Front End IC Designer
Responsibilities:
As an IC designer, you will work on the design and implementation of the company's cutting-edge SoCs, including：
-   Block level design, RTL coding, Verification, Debug, and timing analysis.
-   Top and sub-system level integration, verification, debug, and timing analysis.
-   FPGA validation and Silicon bring-up
Qualification:
-   Master of EE/CS with 3+ years of working experience or BSEE with 5+ years working experience
-   Solid understanding of DSP and communication theory
-   Familiar with Verilog HDL, and matlab/C/C++
-   hands-on experience on IC design and popular EDA tools 
-   Good team player, Self-motivated in solving problems
-   Experience on one or more of the following is a plus:
a)      Mapping algorithm to RTL for various computer arithmetic or signal processing.
b)      Various SoC components, such as CPU/DSP, AMBA bus, USB, I2S, SDIO, SPI, DDR, etc.
good tcl/perl/python scripting skills


前端設(shè)計工程師
職責(zé)描述：
作為前端設(shè)計工程師，您將參與一流的智能語音處理SOC設(shè)計，包括但不限于：
-   模塊級設(shè)計，RTL代碼設(shè)計和驗證
-   子系統(tǒng)集成和驗證
-   綜合和時序分析
-   FPGA 驗證和芯片bring up 
任職資格：
-   電子或計算機相關(guān)專業(yè)碩士畢業(yè)，3年相關(guān)工作經(jīng)驗； 或是本科畢業(yè)，5年相關(guān)工作經(jīng)驗。
-   熟悉數(shù)字信號處理和數(shù)字通信理論
-   精通verilog, matlab和C語言
-   有IC設(shè)計項目經(jīng)驗，熟悉相關(guān)EDA工具 
-   注重團隊合作，善于發(fā)現(xiàn)和解決問題
-   有以下一項或多項經(jīng)驗者優(yōu)先考慮:
a)  信號處理和計算機算法的硬件實現(xiàn)
b)  熟悉CPU/DSP處理器架構(gòu)，以及常見總線和外設(shè)， 如AMBA bus, USB, I2S, SDIO, SPI, DDR等
c)  較好的tcl/perl/python scripting 能力