- 30萬-60萬/年
- 上海
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- 3年以上
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- 本科
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- 全職
職位誘惑: 年終獎金,五險一金,福利好,老板nice,年底雙薪,技能培訓(xùn),節(jié)日禮物,成長空間大,技術(shù)領(lǐng)先
發(fā)布時間: 2022-11-10發(fā)布
職位描述
崗位職責(zé):Job descriptions:1. will work on following Mixed signal IP design: high frequency fractional-N PLL，digital DLL, digital LDO, analog LDO. OSC and high speed interface design.2. work closely with layout designer for layout implementation.3. silicon testing, characterization and debugging.
任職資格:Qualification:1. MSEE 4+ years experience in Mixed signal design.2. Experience in following IP related area: digital PLL/DLL, CDR (phase interpolator), digital LDO, High speed custom logic design and High speed driver/receiver, delta-sigma ADC/DAC, digital low pass filter3. Experience in mixed-signal processing using Matlab is a plus4. Experience in verilog/verilogA coding is a plus.5. Experience in 28n, or FinFet is a plus.6. Familiar with IP views (.LEF, .v, .Lib) is a must.7. Experience in ncverilog/vcs,Spice, Spectre AMS.
職位發(fā)布者
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