崗位職責(zé):
1. Responsible for design verification of cutting edge SoC projects.
2. Participate in all SoC level function verification jobs including: SoC DV testbench and infrastructure development and maintenance
3. Create and execute SoC testplan including data-path and interrupt, security, power management, etc.
4. Implement directed and random test cases in C++/SV, as well as checkers and assertions
5. Help to maintenance and improve DV environment building flow"

任職資格:
1. MS with 5+ years experience in ASIC/SoC design verification
2. Hand-on experience in all domains of complex ASIC DV flow from plan to coverage
3. knowledgeable in Verilog, C, C++ & SV/UVM development, familiar with scripting languages like Perl/shell/tcl etc.
4. Strong problem solving and communication skills, DV lead experience is a big plus
5. Knowledge on computer architecture and high-speed IP interface protocol is preferred
6. Experience in power-aware verification is preferred"