- 25萬-45萬/年
- 上海
- |
- 5年以上
- |
- 本科
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- 全職
職位誘惑: 年終獎金,五險一金,技術(shù)領(lǐng)先,成長空間大,通訊津貼,福利好,年底雙薪,股票期權(quán),天天下午茶,免費班車,技能培訓(xùn)
發(fā)布時間: 2019-03-05發(fā)布
職位描述
1.Develop and support FPGA design for SOC development
2.Responsible for FPGA RTL coding, and migration between ASIC database and FPGA database
3.Responsible for FPGA synthesis/PR timing clean-up and bit file generation
4.Responsible for system-level work and FPGA debug with signal probe tools
Requirements:
1.Bachelor or above degrees in EE/Communication/CS majors with >= 3 years related working experience
2.Must have experiences in digital logic design with Verilog/VHDL...etc.
3.Must have experiences with Xilinx Virtex/Spartan products and familiar with FPGA synthesis flows and tools (ISE, Vivado, Synplify, Chipscope, Protolink…etc)
4.Experience with DDR/ARM/USB FPGA design is a plus.
5.Experience with Synopsys HAPS or equivalent prototype systems is a plus.
職位發(fā)布者
秦遇蛇
Sr.Consultant
簡歷處理用時
簡歷及時處理率
滬公網(wǎng)安備31011502017136號