• Position Description:

    In charge of DDR IP logic design Implementation.
    Daily duties include: RTL coding(plus), Logic Synthesis(must), Static Timing Analysis(must).
    HDL language Knowledge, like verilog or vhdl is necessary. 
    C/C++/perl/tcl/csh/python, UNIX, Linux experience are plus.
    Excellent analytical and problem-solving skills. Quick learner-able to learn and apply technical          and complex topics.
    Excellent communication skills and the uncanny ability in a cooperative team environment are        required.
    Self-motivated, result-oriented, can take ownership and follow-through on tasks.
    Position Requirements:

• Essential Qualifications:

    Master degree with 4~7 years’ experience
    Major in Micro-electronics, Electronic Engineering, Computer Science, Information Technology        or equivalent
    Ability to work effectively alone or as well as in the team.
    Essential that the individual demonstrates strong communication, verbal and written
    Requires good communication skills in English.
    Desirable Qualifications: