Job Title：武漢校招- Digital Design/Verification Engineer (數(shù)字工程師)
Location：Wuhan


基本要求
- 微電子、電子工程、通信或相關(guān)專業(yè)研究生
Typically requires fresh master/PHD graduate with the major of microelectronics, telecommunication, Electrical/Electronic Engineering, or relevance
- 熟悉數(shù)字設(shè)計的基本流程，熟練使用Verilog語言對數(shù)字電路進行設(shè)計或SystemVerilog進行驗證
Familiar with basic digital design flow, experience with Verilog language for digital design or SystemVerilog for verification
- 有使用過腳本語言，如TCL, Perl, Python等
Experience with TCL, Perl, Python, or other scripting languages
崗位關(guān)鍵詞
- 從事的相關(guān)產(chǎn)品是接口控制器 (Interface controller) / 高速DDR PHY /靜態(tài)存儲器/處理器 (Processor) 等
The related products are Interface controller, High Speed DDR PHY, Static memory，Processor etc.
- 使用先進設(shè)計工藝（如5nm/7nm/10nm），從事數(shù)字設(shè)計，UVM驗證，以及業(yè)內(nèi)領(lǐng)先的開發(fā)流程相關(guān)工作，如Timing，DFT, Firmware等相關(guān)工作
Work on Digital Design, UVM Verification, and state-of-the-art implementation flow development including Timing, DFT and Firmware tasks with advanced technology (5nm/7nm/10nm).