數(shù)字后端實(shí)習(xí)生
- 4萬-8萬/年
- 北京
- |
- 應(yīng)屆生/在校生
- |
- 本科
- |
- 實(shí)習(xí)
職位誘惑: 老板nice,技能培訓(xùn),成長(zhǎng)空間大,技術(shù)領(lǐng)先
發(fā)布時(shí)間: 2020-02-28發(fā)布
職位描述
數(shù)字后端實(shí)習(xí)生PD and Power Reductions Intern
Key Responsibilities
1. Power reduction Methodology in Digital physical design
2. Floorplan, Place and Route , Timing/DRC/IR/EM checking/fixing
3. flows/tools methodology
Skills and Experience Requirements
1. Understanding basic ASIC design flow
2. Bachelor and above in microelectronics, or related area
3. With experience on Verilog or System Verilog
4. Sufficient knowledge in Perl/Python/Ruby/Java/C/C++ is a strong plus
5. Nice to have development experience under Linux, knowledge of Shell/Make/VIM/
LOCATION:
Beijing
職位發(fā)布者
AMD
HR
簡(jiǎn)歷處理用時(shí)
簡(jiǎn)歷及時(shí)處理率
推薦朋友
AMD
領(lǐng)域: 移動(dòng)手持,消費(fèi)電子
規(guī)模: 1000人以上
主頁(yè): http://www.amd.com
工作地址:
海淀區(qū)中關(guān)村科學(xué)院南路2號(hào)融科資訊中心C座北路19層
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