- 50萬(wàn)-70萬(wàn)/年
- 上海
- |
- 5年以上
- |
- 碩士
- |
- 全職
職位誘惑: 年終獎(jiǎng)金,五險(xiǎn)一金,福利好,年底雙薪,股票期權(quán)
發(fā)布時(shí)間: 2020-05-28發(fā)布
職位描述
Responsibility：
- As a DFT project leader, you should be work as a chip or sub-chip DFT leader for high performance ASIC design.
- Understand frond-end and back-end design requirement and limitation.
- Support Customer on advance DFT feature requirement.
- Specify the project DFT Design spec.
- Help Block level DFT engineer to resolve key design problem. Develop and maintain project DFT flow.
Requirement:
- 5 years+ DFT experiences and 2 year + top level DFT project experience.
- Deep understanding on DFT Design for large scale and high performance SOC chip design.
- Strong knowledge on STA and Test timing closure.
- 2+ Tapeout ATE bring-up and diagnose experience Massive product ASIC design experience.
- Solid Background on Verilog and SOC design
- Familiar with SNPS and Mentor DFT tools Familiar with PT or Tempus STA tools
- Familiar with simulation and ATE debug Good at makefile, tcl and perl scripts
職位發(fā)布者
Roger Tang 湯馮喆
Recruitment Expert
7天
簡(jiǎn)歷處理用時(shí)
100%
簡(jiǎn)歷及時(shí)處理率
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