In this position, you will work closely with circuit designers both in China and US to perform original, customized analog / mixed signal IC layout.該職位將緊密與中國區(qū)和美國區(qū)的IC設(shè)計(jì)工程師一起去完成新產(chǎn)品的，全定制的模擬和混合信號(hào)IC版圖設(shè)計(jì).
Responsibility崗位職責(zé)：
·         Main responsibility is analog / mixed signal IC layout主要負(fù)責(zé)模擬和混合信號(hào)IC版圖設(shè)計(jì)
·         You will be responsible for all levels of analog mask layout from floor planning, ESD pad placement, block level layout up to top level integration and tape out主要負(fù)責(zé)所有模擬電路版圖的整體布局、靜電保護(hù)設(shè)計(jì)和模塊到頂層的集成設(shè)計(jì)和流片
·         You will communicate and get directions from the analog design engineers to ensure high quality 主要負(fù)責(zé)與模擬IC設(shè)計(jì)工程師溝通并確定方向以確保產(chǎn)品的高質(zhì)量
Requirement 崗位要求：
·         BS degree in electronics or microelectronics engineering or equivalent電子工程學(xué)或微電子學(xué)等專業(yè)，本科及同等學(xué)歷
·         Understand the basic fundamental of electrical engineering具備基本的電子工程知識(shí)
·         Understanding of layout impact on device matching, noise coupling from signal, supply and substrate 知曉版圖設(shè)計(jì)對器件匹配，信號(hào)干擾，信號(hào)線及襯底的影響
·         Understanding basic characteristics of transistor, resistor, capacitor and diode 具備基本的晶體管、電阻器、電容器和二極管知識(shí)
·         Understanding the importance of signal flow, power/ground structure and block placement in layout floor planning知曉信號(hào)走向，電源及地線結(jié)構(gòu)和模塊頂層布局的重要性
·         Understanding the importance of communication with analog designers知曉該工作與模擬電路設(shè)計(jì)師溝通的重要性
·         Must be familiar with DRC/LVS verification tools需熟悉DRC/LVS等驗(yàn)證工具
·         Must be familiar with Unix OS 需熟練操作Unix OS系統(tǒng)
·         Must be familiar with layout tools, such as Cadence Virtuoso, etc.需熟練操作Layout 工具，如：Cadence Virtuoso等
·         English, written and verbal, sufficient for technical discussions英語讀寫流利，能進(jìn)行技術(shù)交流和溝通