DFT 需要不斷進化和創(chuàng)新來應(yīng)對新工藝新需求，目前，DFT 已經(jīng)轉(zhuǎn)變?yōu)槎嗑S度的 DFX，關(guān)于什么是 DFX, 一個公式告訴你：
DFX = DFT+DFM+DFR+DFD+……
DFT：Design for Testability
DFM: Design for Manufacturability
DFR: Design for Reliability
DFD: Design for Debug

在 NVIDIA DFX 團隊，聚集著來自全球各地的專家及優(yōu)秀人才，若想體驗全球化的團隊協(xié)作，這里一定是不二之選。在這里，你可以搶先見證最前沿且持續(xù)創(chuàng)新的 DFT / DFX 技術(shù)。這里有強大的設(shè)計和驗證平臺，為一次流片成功提供強有力的支持。除此之外，NVIDIA DFX 團隊擁有開放的企業(yè)文化，同時還為團隊成員提供了更多的職業(yè)發(fā)展機會。

目前，NVIDIA 上海 DFX 團隊已擁有各個領(lǐng)域的技術(shù)專家，具備獨立完成芯片 DFT 設(shè)計和實現(xiàn)的能力，在全球團隊中引領(lǐng) DFT 的設(shè)計驗證工作。該團隊在上海設(shè)有 ATE lab 和 ATE 測試機臺，可以第一時間解決芯片生產(chǎn)初期 bringup 的問題，從而實現(xiàn)為芯片量產(chǎn)加速。

你將參與 GPU 和 Tegra 產(chǎn)品線的研發(fā)，與 SOC、PD、PR 等團隊配合，完成 DFT 從 RTL 到 tape out 的芯片實現(xiàn)工作；與 TE、PE 等團隊合作，完成芯片 ATE bringup 工作。

未來，你將負責(zé)以下一項或多項具體工作內(nèi)容：
• JTAG 1500 / 1687
• DFT Clock
• DFT Insertion
• ATPG
• BIST (MBIST, LBIST, etc.)
• IST and Online Test
• ATE Bringup
• DFT Design / Methodology
• DFT Infrastructure / Flow Development

【我們期待這樣的你】
• 了解 DFT 的主要技術(shù)，具備 Scan / ATPG / BIST / JTAG / Clocks / Bringup 等任一方向工作經(jīng)驗（對 NCG 或 Intern 可不做要求）
• 熟悉 Tcl、Perl、Python 等腳本語言
• 有數(shù)字芯片前端或后端設(shè)計經(jīng)驗為加分項
• 良好的英語讀寫和口語交流能力
• 敢于接受挑戰(zhàn)，富有創(chuàng)新精神

JD
We are now looking for a DFT Engineer.

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.

Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

What you'll be doing:

DFT planning, implementation, verification and silicon bring up at IP or fullchip level for all of NVIDIA's semiconductor products.

Take lead role of some DFT areas in a project.

Improve DFT design, architecture and flow.

What we need to see:

Familiar with Verilog and ASIC design.

Proven knowledge and expertise in JTAG, Scan, BIST including memories and IOs, ATPG, fault models and fault simulation, etc.

Excellent analytical skills in verification and validation of test patterns and logic on sophisticated VLSI designs.

Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs.

Experience in silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing and diagnostics.

Strong programming and scripting skills in Perl, Python or Tcl desired.

Outstanding written and oral communication skills in English with the curiosity to work on rare challenges.